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functional block diagrams in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg511 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg512 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg513 switches shown for a logic "1" input rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos precision 5 v/3 v quad spst switches adg511/adg512/adg513 features +3 v, +5 v or 5 v power supplies ultralow power dissipation (<0.5 w) low leakage (<100 pa) low on resistance (<50 ) fast switching times low charge injection ttl/cmos compatible 16-lead dip or soic package applications battery-powered instruments single supply systems remote powered equipment 5 v supply systems computer peripherals such as disk drives precision instrumentation audio and video switching automatic test equipment precision data acquisition sample hold systems communication systems compatible with 5 v supply dacs and adcs such as ad7840/ad7848, ad7870/ad7871/ad7872/ad7874/ ad7875/ad7876/ad7878 general description the adg511, adg512 and adg513 are monolithic cmos ics containing four independently selectable analog switches. these switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. these switch arrays are fabricated using analog devices advanced linear compatible cmos (lc 2 mos) process which offers the additional benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. these features make the adg511, adg512 and adg513 the optimum choice for a wide variety of signal switching tasks in precision analog signal processing and data acquisition systems. the ability to operate from single +3 v, +5 v or 5 v bipolar supplies make the adg511, adg512 and adg513 perfect for use in battery-operated instruments, 4?0 ma loop systems and with the new generation of dacs and adcs from analog devices. the use of 5 v supplies and reduced operating currents give much lower power dissipation than devices operating from 15 v supplies. the adg511, adg512 and adg513 contain four indepen- dent spst switches. the adg511 and adg512 differ only in that the digital control logic is inverted. the adg511 switch is turned on with a logic low on the appropriate control input, while a logic high is required for the adg512. the adg513 contains two switches whose digital control logic is similar to that of the adg511 while the logic is inverted in the remaining two switches. product highlights 1. 5 volt single supply operation the adg511/adg512/adg513 offers high performance, including low on resistance and wide signal range, fully specified and guaranteed with +3 v, 5 v as well as +5 v supply rails. 2. ultralow power dissipation cmos construction ensures ultralow power dissipation. 3. low r on 4. break-before-make switching switches are guaranteed to have break-before-make opera- tion. this allows multiple outputs to be tied together for multiplexer applications without the possibility of momen tary shorting between channels. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001
dual supply b versions t version ?0 c to ?5 c to parameter 25 c +85 c25 c +125 c unit test conditions/comments analog switch analog signal range v dd to v ss v dd to v ss v r on 30 30 ? typ v d = 3.5 v, i s = ?0 ma; 50 50 ? max v dd = +4.5 v, v ss = ?.5 v leakage currents v dd = +5.5 v, v ss = ?.5 v source off leakage i s (off) 0.025 0.025 na typ v d = 4.5 v, v s = 4.5 v; 0.1 2.5 0.1 2.5 na max test circuit 2 drain off leakage i d (off) 0.025 0.025 na typ v d = 4.5 v, v s = 4.5 v; 0.1 2.5 0.1 2.5 na max test circuit 2 channel on leakage i d , i s (on) 0.05 0.05 na typ v d = v s = 4.5 v; 0.2 5 0.2 5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 0.005 0.005 a typ v in = v inl or v inh 0.1 0.1 a max dynamic characteristics 2 t on 200 200 ns typ r l = 300 ? . c l = 35 pf; 375 375 ns max v s = 3 v; test circuit 4 t off 120 120 ns typ r l = 300 ? . c l = 35 pf; 150 150 ns max v s = 3 v; test circuit 4 break-before-make time 100 100 ns typ r l = 300 ? , c l = 35 pf; delay, t d (adg513 only) v s1 = v s2 = 3 v; test circuit 5 charge injection 11 11 pc typ v s = 0 v, r s = 0 ? , c l = 10 nf; test circuit 6 off isolation 68 68 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk 85 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 9 9 pf typ f = 1 mhz c d (off) 9 9 pf typ f = 1 mhz c d , c s (on) 35 35 pf typ f = 1 mhz power requirements v dd +4.5/5.5 +4.5/5.5 v min/max v ss ?.5/?.5 ?.5/?.5 v min/max i dd 0.0001 0.0001 a typ v dd = +5.5 v, v ss = ?.5 v 11 a max digital inputs = 0 v or 5 v i ss 0.0001 0.0001 a typ 11 a max notes 1 temperature ranges are as follows: b versions ?0 c to +85 c; t version ?5 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. rev. c C2C (v dd = +5 v 10%, v ss = ? v 10%, gnd = 0 v, unless otherwise noted) adg511/adg512/adg513?pecifications 1
single supply b versions t version ?0 c to ?5 c to parameter 25 c +85 c25 c +125 c unit test conditions/comments analog switch analog signal range 0 v to v dd 0 v to v dd v r on 45 45 ? typ v d = 3.5 v, i s = ?0 ma; 75 75 ? max v dd = 4.5 v leakage currents v dd = 5.5 v source off leakage i s (off) 0.025 0.025 na typ v d = 4.5/1 v, v s = 1 4.5 v; 0.1 2.5 0.1 2.5 na max test circuit 2 drain off leakage i d (off) 0.025 0.025 na typ v d = 4.5/1 v, v s = 1 4.5 v; 0.1 2.5 0.1 2.5 na max test circuit 2 channel on leakage i d , i s (on) 0.05 0.05 na typ v d = v s = 4.5 v/1 v; 0.2 5 0.2 5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 0.005 0.005 a typ v in = v inl or v inh 0.1 0.1 a max dynamic characteristics 2 t on 250 250 ns typ r l = 300 ? , c l = 35 pf; 500 500 ns max v s = 2 v; test circuit 4 t off 50 50 ns typ r l = 300 ? , c l = 35 pf; 100 100 ns max v s = 2 v; test circuit 4 break-before-make time 200 200 ns typ r l = 300 ? , c l = 35 pf; delay, t d (adg513 only) v s1 = v s2 = 2 v; test circuit 5 charge injection 16 16 pc typ v s = 0 v, r s = 0 ? , c l = 10 nf; test circuit 6 off isolation 68 68 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk 85 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 9 9 pf typ f = 1 mhz c d (off) 9 9 pf typ f = 1 mhz c d , c s (on) 35 35 pf typ f = 1 mhz power requirements v dd 4.5/5.5 4.5/5.5 v min/max i dd 0.0001 0.0001 a typ v dd = 5.5 v 11 a max digital inputs = 0 v or 5 v notes 1 temperature ranges are as follows: b versions ?0 c to +85 c; t version ?5 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted) adg511/adg512/adg513 rev. c C3C
single supply b version 0 c to parameter 25 c70 c unit test conditions/comments analog switch analog signal range 0 v to v dd v r on 200 ? typ v d = 1.5 v, i s = ? ma; 500 ? max v dd = 3 v leakage currents v dd = 3.6 v source off leakage i s (off) 0.025 na typ v d = 2.6/1 v, v s = 1 2.6 v; 0.1 2.5 na max test circuit 2 drain off leakage i d (off) 0.025 na typ v d = 2.6/1 v, v s = 1 2.6 v; 0.1 2.5 na max test circuit 2 channel on leakage i d , i s (on) 0.05 na typ v d = v s = 2.6 v/1 v; 0.2 5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max dynamic characteristics 2 t on 600 ns typ r l = 300 ? , c l = 35 pf; 1200 ns max v s = 1 v; test circuit 4 t off 100 ns typ r l = 300 ? , c l = 35 pf; 160 ns max v s = 1 v; test circuit 4 break-before-make time 500 ns typ r l = 300 ? , c l = 35 pf; delay, t d (adg513 only) v s1 = v s2 = 1 v; test circuit 5 charge injection 11 pc typ v s = 0 v, r s = 0 ? , c l = 10 nf; test circuit 6 off isolation 68 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 9 pf typ f = 1 mhz c d (off) 9 pf typ f = 1 mhz c d , c s (on) 35 pf typ f = 1 mhz power requirements v dd 3/3.6 v min/max i dd 0.0001 a typ v dd = 3.6 v 1 a max digital inputs = 0 v or 3 v notes 1 temperature range is as follows: b version ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. rev. c C4C adg511/adg512/adg513?pecifications 1 (v dd = 3.3 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted)
adg511/adg512/adg513 rev. c C5C absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?5 v analog, digital inputs 2 . . . . . . . . . . v ss ?2 v to v dd + 2 v or 30 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . ?0 c to +85 c extended (t version) . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c cerdip package, power dissipation . . . . . . . . . . . . . . . 900 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 76 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 300 c plastic package, power dissipation . . . . . . . . . . . . . . . 470 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 117 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 260 c soic package, power dissipation . . . . . . . . . . . . . . . . 600 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 77 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg511/adg512/adg513 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model 1 temperature range 2 package option 3 adg511bn ?0 c to +85 c n-16 adg511br ?0 c to +85 c r-16a adg511abr 4 ?0 c to +85 c r-16a adg511tq 4 ?5 c to +125 c q-16 adg512bn ?0 c to +85 c n-16 adg512br ?0 c to +85 c r-16a adg512abr 4 ?0 c to +85 c r-16a adg513bn ?0 c to +85 c n-16 adg513br ?0 c to +85 c r-16a adg513abr 4 ?0 c to +85 c r-16a notes 1 for availability of mil-std-883, class b processed parts, contact factory. 2 3.3 v specifications apply over 0 c to 70 c temperature range. 3 n = plastic dip; r = 0.15" small outline ic (soic); q = cerdip. 4 trench isolated latch-up proof parts. see trench isolation section. warning! esd sensitive device
adg511/adg512/adg513 rev. c C6C pin configuration (dip/soic) top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 d1 s1 v ss gnd s4 d4 in4 in2 d2 s2 v dd nc s3 d3 in3 adg511 adg512 adg513 nc = no connect truth table (adg511/adg512) adg511 adg512 switch in in condition 01 on 1 0 off truth table (adg513) switch switch logic 1, 4 2, 3 0 off on 1 on off terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to gnd. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. i s (off) source leakage current with the switch ?ff. i d (off) drain leakage current with the switch ?ff. i d , i s (on) channel leakage current with the switch ?n. v d (v s ) analog voltage on terminals d, s. c s (off) ?ff?switch source capacitance. c d (off) ?ff?switch drain capacitance. c d , c s (on) ?n?switch capacitance. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. t d ?ff?or ?n?time measured between the 90% points of both switches when switching from one address state to another. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an ?ff?switch. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching.
v d or v s ?drain or source voltage ?v 50 40 0 ? 5 ? r on ? ? ? ? 0 1234 30 20 10 t a = 25 c v dd = +3v v ss = ?v v dd = +5v v ss = ?v tpc 1. on resistance as a function of v d (v s ) dual supplies v d or v s drain or source voltage v 50 40 0 55 4 r on 3 2 1 0 1234 30 20 10 v dd = +5v v ss = 5v 125 c 85 c 25 c tpc 2. on resistance as a function of v d (v s ) for different temperatures v d or v s drain or source voltage v 90 80 20 05 1 r on 234 60 50 40 30 70 t a = 25 c v dd = 3v v ss = 0v v dd = 5v v ss = 0v tpc 3. on resistance as a function of v d (v s ) single supply typical performance characteristics adg511/adg512/adg513 rev. c C7C frequency hz 10ma 10 a 10na 10m 10 i supply 100 1k 10k 100k 1m 1ma 100 a 1 a 100na v dd = +5v v ss = 5v i , i+ 1 sw 4 sw ()% .
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1 temperature c 10 1 0.001 25 125 35 leakage current na 45 55 65 75 85 95 105 115 0.1 0.01 v dd = +5v v ss = 5v v s = 5v v d = 5v i d (off) i d (on) i s (off) ()& 23
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frequency hz 120 100 40 100 10m 1k off isolation db 10k 100k 1m 80 60 v dd = +5v v ss = 5v tpc 6. off isolation vs. frequency
adg511/adg512/adg513 rev. c C8C v d or v s drain or source voltage v 0.006 0.000 0.006 5 leakage current na 0.004 0.002 0.002 0.004 v dd = +5v v ss = 5v t a = +25 c i d (off) i d (on) i s (off) 4 3 2 101234 5 tpc 7. leakage currents as a function of v d (v s ) frequency hz 110 100 60 100 10m 1k crosstalk db 10k 100k 1m 90 80 70 v dd = +5v v ss = 5v tpc 8. crosstalk vs. frequency application figure 1 illustrates a precise sample-and-hold circuit. an ad845 is used as the input buffer while the output operational ampli- fier is an op07. during the track mode, sw1 is closed and the output v out follows the input signal v in . in the hold mode, sw1 is opened and the signal is held by the hold capacitor c h . due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. the adg511/adg512/ adg513 minim izes this droop due to its low leakage specifica- tions. the droop rate is further minimized by the use of a poly- styrene hold capacitor. the droop rate for the circuit shown is typically 15 v/ s. a second switch, sw2, which operates in parallel with sw1, is included in this circuit to reduce pedestal error. since both switches will be at the same potential, they will have a differen- tial effect on the op amp op07, which will minimize charge injection effects. pedestal error is also reduced by the compensation network r c and c c . this compensation network also reduces the hold time glitch while optimizing the acquisition time. using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mv over the 3 v input range. the acquisition time is 2.5 s while the settling time is 1.85 s. +5v 5v 2200pf r c 75 c c 1000pf c h 2200pf v out adg511/ adg512/ adg513 sw1 sw2 s s d d +5v 5v ad845 +5v 5v v in op07 figure 1. accurate sample-and-hold trench isolation the mos devices that make up the adg511a/adg512a/ adg513a are isolated from each other by an oxide layer (trench) (see figure 2). when the nmos and pmos devices are not electrically isolated from each other, there exists the possibility of ?atch-up?caused by parasitic junctions between cmos transistors. latch-up is caused when p-n junctions that are normally reverse biased, become forward biased, causing large currents to flow. this can be destructive. cmos devices are normally isolated from each other by junction isolation . in junction isolation the n and p wells of the cmos tran sistors form a diode that is reverse biased under normal operation. however, during overvoltage conditions, this diode becomes forward biased. a silicon-controlled rectifier (scr)- type circuit is formed by the two transistors, causing a signifi- cant amplification of the current that, in turn, leads to latch-up. with trench isolation, this diode is rem oved; the result is a latch-up-proof circuit. buried oxide layer substrate (backgate) t r e n c h t r e n c h t r e n c h p + p + p-channel n + n + n-channel p n v g v d v s v g v d v s figure 2. trench isolation
adg511/adg512/adg513 rev. c C9C i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance sd v s a v d a i s (off) i d (off) test circuit 2. off leakage sd v s v d a i d (on) (
$ +23 sd v dd 0.1 f v dd in v s gnd v ss r l 300 c l 35pf v out 0.1 f v ss t on t off 3v 50% 50% 50% 50% 3v 90% 90% v in v in v out adg511 adg512 test circuit 4. switching times s1 d1 0.1 f v dd in1, in2 v s1 gnd v ss r l1 300 c l1 35pf v out1 0.1 f v s2 v out2 r l2 300 c l2 35pf s2 v in d2 v dd v ss t d t d 3v 50% 50% 90% v in v out1 v out2 90% 90% 90% 0v 0v 0v test circuit 5. break-before-make time delay sd v dd in v s gnd v ss c l 10nf v out r s v ss v dd 3v v in v out v out q inj = c l v out test circuit 6. charge injection test circuits
adg511/adg512/adg513 rev. c C10C sd 0.1 f v dd in v s gnd v ss r l 50 v out 0.1 f v in v ss v dd test circuit 7. off isolation sd 0.1 f v dd v s gnd v ss 50 nc 0.1 f v in1 v in2 s d r l 50 v out channel-to-channel crosstalk = 20 log v s /v out v dd v ss test circuit 8. channel-to-channel crosstalk
adg511/adg512/adg513 rev. c C11C outline dimensions dimensions shown in inches and (mm). 16-lead plastic dip (n-16) 16 18 9 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead cerdip (q-16) 16 1 8 9 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.080 (2.03) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 16-lead soic (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
c00036bC0C5/01(c) printed in u.s.a. C12C adg511/adg512/adg513 revision history rev. c location page data sheet changed from rev. b to rev. c. changes to specifications table, dual supply, and notes: ? versions?made singular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to specifications table, single supply, and notes: ? versions?made singular . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 change to ordering guide: removed one line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

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